R10000 Microprocessor User's Manual

10. CACHE Instructions

This chapter describes the CacheOps (CACHE*1) used in the R10000 processor.

The format of the CACHE instruction is:

CACHE op, offset(base)

In a CACHE instruction, the 16-bit offset is sign-extended and added to the contents of the general register base to form a Virtual Address (VA). The VA is translated to a Physical Address (PA) using the TLB. The 5-bit sub-opcode specifies a cache instruction variation for that address.

Chapter Contents

10.1 - Notes on CACHE Instruction Operations
10.2 - Index Invalidate (I)
10.3 - Index WriteBack Invalidate (D)
10.4 - Index WriteBack Invalidate (S)
10.5 - Index Load Tag (I)
10.6 - Index Load Tag (D)
10.7 - Index Load Tag (S)
10.8 - Index Store Tag (I)
10.9 - Index Store Tag (D)
10.10 - Index Store Tag (S)
10.11 - Hit Invalidate (I)
10.12 - Hit Invalidate (D)
10.13 - Hit Invalidate (S)
10.14 - Cache Barrier
10.15 - Hit Writeback Invalidate (D)
10.16 - Hit WriteBack Invalidate (S)
10.17 - Index Load Data (I)
10.18 - Index Load Data (D)
10.19 - Index Load Data (S)
10.20 - Index Store Data (I)
10.21 - Index Store Data (D)
10.22 - Index Store Data (S)

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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